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FQS4900
August 2000
QFET
FQS4900
Dual N & P-Channel, Logic Level MOSFET
General Description
These dual N and P-channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. This device is well suited for high interface in telephone sets.
TM
Features
* N-Channel 1.3A, 60V, RDS(on) = 0.55 @ VGS = 10 V RDS(on) = 0.65 @ VGS = 5 V P-Channel -0.3A, -300V, RDS(on) = 15.5 @ VGS = -10 V RDS(on) = 16 @ VGS =- 5 V * Low gate charge ( typical N-Channel 1.6 nC) ( typical P-Channel 3.6 nC) * Fast switching * Improved dv/dt capability
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D2 D2 D1 D1
6
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Absolute Maximum Ratings
Symbol VDSS ID IDM VGSS dv/dt PD TJ, TSTG
TA = 25C unless otherwise noted
Parameter Drain-Source Voltage - Continuous (TA = 25C) Drain Current - Continuous (TA = 70C) Drain Curent - Pulsed
(Note 1)
N-Channel 60 1.3 0.82 5.2 20
(Note 2)
P-Channel -300 -0.3 -0.19 -1.2 4.5 2.0 1.3
Units V A A A V V/ns W W C
Gate-Source Voltage Peak Diode Recovery dv/dt Power Dissipation (TA = 25C) (TA = 70C) Operating and Storage Temperature Range
7.0
-55 to +150
Thermal Characteristics
Symbol RJA Parameter Thermal Resistance, Junction-to-Ambient Typ -Max 62.5 Units C/W
(c)2000 Fairchild Semiconductor International
Rev. A, August 2000
FQS4900
Electrical Characteristics
Symbol Parameter
TA = 25C unless otherwise noted
Test Conditions
Type
Min
Typ
Max
Units
Off Characteristics
BVDSS IDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 A VGS = 0 V, ID = -250 A Zero Gate Voltage Drain Current VDS = 60 V, VGS = 0 V VDS = 48 V, TC = 55C VDS = -300 V, VGS = 0 V VDS = -240 V, TC = 55C IGSSF IGSSR Gate-Body Leakage Current, Forward Gate-Body Leakage Current, Reverse VGS = 20 V, VDS = 0 V VGS = -20 V, VDS = 0 V N-Ch P-Ch N-Ch P-Ch All All 60 -300 ----------------1 10 -1 -10 100 -100 V V A A A A nA nA
On Characteristics
VGS(th) RDS(on) Gate Threshold Voltage Static Drain-Source On-Resistance VDS = 4V, ID = 20 mA VDS = 4V, ID = -20 mA VGS = 10 V, ID = 0.65 A VGS = 5 V, ID = 0.65 A VGS = -10 V, ID = -0.15 A VGS = -5 V, ID = -0.15 A gFS Forward Transconductance VDS = 10 V, ID = 0.65 A VDS = -10 V, ID = -0.15 A N-Ch P-Ch N-Ch P-CH N-CH P-CH 1.0 -1.0 --------0.39 0.46 11.2 11.4 1.7 0.6 1.95 -1.95 0.55 0.65 15.5 16 --V V S S
Switching Characteristics
td(on) tr td(off) tf Qg Qgs Qgd Turn-On Delay Time Turn-On Rise Time Turn-Off Delay Time Turn-Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge N-Channel VDD = 30 V, ID = 1.3 A, RG = 25 P-Channel VDD = -150 V, ID = -0.3 A, RG = 25 N-Channel VDS = 48 V, ID = 1.3 A, VGS = 5 V P-Channel VDS = -240 V, ID = -0.3 A, VGS = -5 V N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch --------------5.7 10 21 25 11 35 17 47 1.6 3.6 0.28 0.42 0.82 2.1 21 30 50 60 32 80 45 105 2.1 4.7 ----ns ns ns ns ns ns ns ns nC nC nC nC nC nC
Drain-Source Diode Characteristics and Maximum Ratings
IS VSD Maximum Continuous Drain-Source Diode Forward Current Drain-Source Diode Forward Voltage VGS = 0 V, IS = 1.3 A VGS = 0 V, IS = -0.3 A
Notes: 1. Repetitive Rating : Pulse width limited by maximum junction temperature 3. Pulse Test : Pulse width 300s, Duty cycle 2% 4. Essentially independent of operating temperature
N-Ch P-Ch N-Ch P-Ch
-----
-----
1.3 -0.3 1.5 -4.0
A A V V
(c)2000 Fairchild Semiconductor International
Rev. A, August 2000
FQS4900
Typical Characteristics : N-Channel
10
0
ID, Drain Current [A]
ID, Drain Current [A]
VGS 10.0 V 8.0 V 6.0 V 5.0 V 4.5 V 4.0 V 3.5 V Bottom : 3.0 V Top :
10
0
150
25 -55
Notes : 1. VDS = 25V 2. 250 s Pulse Test
Notes : 1. 250 s Pulse Test 2. TC = 25
10
-1
10
-1
10
0
10
1
10
-1
0
2
4
6
8
10
VDS, Drain-Source Voltage [V]
VGS, Gate-Source Voltage [V]
Figure 1. On-Region Characteristics
Figure 2. Transfer Characteristics
2.0
RDS(ON) [ ], Drain-Source On-Resistance
IDR , Reverse Drain Current [A]
1.5
VGS = 10V
VGS = 5V
1.0
10
0
150
25
Notes : 1. VGS = 0V 2. 250 s Pulse Test
0.5
Note : TJ = 25
0.0 0 2 4 6 8
10
-1
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
ID, Drain Current [A]
VSD, Source-Drain voltage [V]
Figure 3. On-Resistance Variation vs. Drain Current and Gate Voltage
Figure 4. Body Diode Forward Voltage Variation vs. Source Current and Temperature
12 160
Ciss = Cgs + Cgd (Cds = shorted) Coss = Cds + Cgd Crss = Cgd
10
120
Capacitance [pF]
Ciss Coss
80
Notes : 1. VGS = 0 V 2. f = 1 MHz
VGS, Gate-Source Voltage [V]
8
VDS = 30V VDS = 48V
6
4
40
Crss
2
Note : ID = 1.3 A
0 -1 10
10
0
10
1
0 0.0
0.5
1.0
1.5
2.0
2.5
3.0
VDS, Drain-Source Voltage [V]
QG, Total Gate Charge [nC]
Figure 5. Capacitance Characteristics
Figure 6. Gate Charge Characteristics
(c)2000 Fairchild Semiconductor International
Rev. A, August 2000
FQS4900
Typical Characteristics : N-Channel (Continued)
1.2
2.5
BV DSS , (Normalized) Drain-Source Breakdown Voltage
2.0
RDS(ON) , (Normalized) Drain-Source On-Resistance
1.1
1.5
1.0
1.0
0.9
Notes : 1. VGS = 0 V 2. ID = 250 A
0.5
Notes : 1. VGS = 10 V 2. ID = 0.65 A
0.8 -100
-50
0
50
100
o
150
200
0.0 -100
-50
0
50
100
o
150
200
TJ, Junction Temperature [ C]
TJ, Junction Temperature [ C]
Figure 7. Breakdown Voltage Variation vs. Temperature
Figure 8. On-Resistance Variation vs. Temperature
1.5
Operation in This Area is Limited by R DS(on)
10
1
1.2
ID, Drain Current [A]
10 ms
10
0
ID, Drain Current [A]
2
1 ms
100 ms 1s 10 s DC
0.9
0.6
10
-1
Notes : 1. TC = 25 C 2. TJ = 150 C 3. Single Pulse
o o
0.3
10
-2
10
-1
10
0
10
1
10
0.0 25
50
75
100
125
150
VDS, Drain-Source Voltage [V]
TC, Case Temperature []
Figure 9. Maximum Safe Operating Area
Figure 10. Maximum Drain Current vs. Case Temperature
( t) , T h e r m a l R e s p o n s e
D = 0 .5 0 .2 0 .1 0 .0 5 0 .0 2
10
0
10
1
N o te s : 1 . Z J C ( t) = 6 2 . 5 /W M a x . 2 . D u ty F a c to r , D = t 1 / t 2 3 . T J M - T C = P D M * Z J C ( t)
0 .0 1
Z
JC
PDM
s in g le p u ls e
10
-1
t1 t2
10
-1
10
-4
10
-3
10
-2
10
0
10
1
10
2
t 1 , S q u a r e W a v e P u ls e D u r a tio n [s e c ]
Figure 11. Transient Thermal Response Curve
(c)2000 Fairchild Semiconductor International
Rev. A, August 2000
FQS4900
Typical Characteristics : P-Channel (Continued)
10
0
-I D , Drain Current [A]
-I D, Drain Current [A]
10
-1
VGS -10.0 V -8.0 V -6.0 V -5.0 V -4.5 V -4.0 V -3.5 V Bottom : -3.0 V Top :
10
0
150
25 -55
Notes : 1. VDS = -25V 2. 250 s Pulse Test
10
-2
Notes : 1. 250 s Pulse Test 2. TC = 25
10
-1
10
0
10
1
10
-1
0
2
4
6
8
10
-VDS, Drain-Source Voltage [V]
-VGS , Gate-Source Voltage [V]
Figure 1. On-Region Characteristics
Figure 2. Transfer Characteristics
30
10
0
RDS(on) [], Drain-Source On-Resistance
VGS = - 5V
20
VGS = - 10V
15
Note : TJ = 25
-I DR , Reverse Drain Current [A]
25
150 25
Notes : 1. VGS = 0V 2. 250 s Pulse Test
10 0.0
10
-1
0.3
0.6
0.9
1.2
1.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
-ID , Drain Current [A]
-VSD , Source-Drain Voltage [V]
Figure 3. On-Resistance Variation vs. Drain Current and Gate Voltage
Figure 4. Body Diode Forward Voltage Variation vs. Source Current and Temperature
250
Ciss = Cgs + Cgd (Cds = shorted) Coss = Cds + Cgd Crss = Cgd
12
200
10
-V GS , Gate-Source Voltage [V]
8
VDS = -60V VDS = -150V
Capacitance [pF]
150
Ciss
6
100
Coss
Notes :
VDS = -240V
4
50
Crss
1. VGS = 0 V 2. f = 1 MHz
2
Note : ID = -0.3 A
0 -1 10
0 10
0
10
1
0
1
2
3
4
5
6
VDS, Drain-Source Voltage [V]
QG, Total Gate Charge [nC]
Figure 5. Capacitance Characteristics
Figure 6. Gate Charge Characteristics
(c)2000 Fairchild Semiconductor International
Rev. A, August 2000
FQS4900
Typical Characteristics : P-Channel (Continued)
1.2
2.5
-BV DSS , (Normalized) Drain-Source Breakdown Voltage
2.0
RDS(ON) , (Normalized) Drain-Source On-Resistance
1.1
1.5
1.0
1.0
0.9
Notes : 1. VGS = 0 V 2. ID = -250 A
0.5
Notes : 1. VGS = -10 V 2. ID = -0.15 A
0.8 -100
-50
0
50
100
o
150
200
0.0 -100
-50
0
50
100
o
150
200
TJ, Junction Temperature [ C]
TJ, Junction Temperature [ C]
Figure 7. Breakdown Voltage Variation vs. Temperature
Figure 8. On-Resistance Variation vs. Temperature
10
1
0.35
Operation in This Area is Limited by R DS(on)
0.30
10
0
100 ms 1s
10
-1
-I D, Drain Current [A]
-I D, Drain Current [A]
10 ms
1 ms
0.25
0.20
10 s DC
0.15
10
-2
0.10
Notes : 1. TC = 25 C 2. TJ = 150 C 3. Single Pulse
o o
0.05
10
-3
10
0
10
1
10
2
0.00 25
50
75
100
125
150
-VDS, Drain-Source Voltage [V]
TC, Case Temperature []
Figure 9. Maximum Safe Operating Area
Figure 10. Maximum Drain Current vs. Case Temperature
( t) , T h e r m a l R e s p o n s e
D = 0 .5 0 .2 0 .1 0 .0 5 0 .0 2
10
0
10
1
N o te s : 1 . Z J C ( t) = 6 2 . 5 /W M a x . 2 . D u ty F a c to r , D = t 1 / t 2 3 . T J M - T C = P D M * Z J C ( t)
0 .0 1
Z
JC
PDM
s in g le p u ls e
10
-1
t1 t2
10
-1
10
-4
10
-3
10
-2
10
0
10
1
10
2
t 1 , S q u a r e W a v e P u ls e D u r a tio n [s e c ]
Figure 11. Transient Thermal Response Curve
(c)2000 Fairchild Semiconductor International
Rev. A, August 2000
FQS4900
Gate Charge Test Circuit & Waveform
50K 12V 200nF 300nF
Same Type as DUT VDS
VGS Qg 5V Qgs Qgd
VGS
DUT
3mA
Charge
Resistive Switching Test Circuit & Waveforms
VDS VGS RG
RL VDD
VDS
90%
5V
DUT
VGS
10%
td(on) t on
tr
td(off) t off
tf
(c)2000 Fairchild Semiconductor International
Rev. A, August 2000
FQS4900
Package Dimensions
8-SOP
MIN 1.55 0.20 0.061 0.008 0.1~0.25 0.004~0.001
#1
#8 4.92 0.20 0.194 0.008 5.13 MAX 0.202
( #4 #5 6.00 0.30 0.236 0.012
+0.10 0.15 -0.05 +0.004 0.006 -0.002
0.56 ) 0.022 1.80 MAX 0.071 MAX0.10 MAX0.004 3.95 0.20 0.156 0.008 5.72 0.225 0.50 0.20 0.020 0.008
(c)2000 Fairchild Semiconductor International
0~
8
1.27 0.050
Rev. A, August 2000
0.41 0.10 0.016 0.004
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
ACExTM BottomlessTM CoolFETTM CROSSVOLTTM E2CMOSTM FACTTM FACT Quiet SeriesTM FAST(R) FASTrTM GTOTM
HiSeCTM ISOPLANARTM MICROWIRETM POPTM PowerTrench(R) QFETTM QSTM Quiet SeriesTM SuperSOTTM-3 SuperSOTTM-6
SuperSOTTM-8 SyncFETTM TinyLogicTM UHCTM VCXTM
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR INTERNATIONAL. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS Definition of Terms
Datasheet Identification Advance Information Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Preliminary
No Identification Needed
Full Production
Obsolete
Not In Production
(c)2000 Fairchild Semiconductor International
Rev. A, January 2000

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